Push-pull Clocked Logic
This page has details about clock logic using the push-pull flip-flop logic gate described elsewhere on this site.
If you look at any digital electronic book, you'll soon see that anything
useful tends to make use of a clock pulse to synchronise everything. The clock
input is separate from the logic inputs, but they are related. A simple way to
implement a clock is by using two NAND gates. Doing this changes the set and
clear operations from working on a 0 to 1 transition to working on a 0 to 1
transition. The clocked Flip-Flop examples should show what's happening along with their descriptions below.
The initial set up of the FF, Set, Clock (clk), Clear and Qbar are at a logic level of 0 and Q is 1.
Pulse Clear to 1, then pulse to Clock (clk) to 1. This makes Q=0 and Qbar=1.
Just as before the right hand NAND output is 1, so the Clear will have no effect
on either Q or Qbar.
The Clock goes to 0 and then Clear goes to 0. It has to be done in this order
to prevent the outputs becoming indeterminate.
Now pulse Set to 1 and the clk to 1. This turns Q=1 and Qbar=0. The left hand
NAND gate output is 1 and so changing the value of Set will not do anything.
The Clock goes to 0 and then Set goes to 0. Just as before it has to be done in this order
to present the outputs becoming indeterminate.
It is possible to build an edge detector for the Clock signal. It requires a
few more NAND gates. The advantage of doing this is that it no longer matters
when the Clock signal goes back to 0 and the indeterminate state is avoided.